1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a selecting circuit for selecting a memory cell based on an address signal in a semiconductor memory device.
2. Description of the Background Art
When a memory cell is selected in a semiconductor memory device, for example in a DRAM (Dynamic Random Access Memory), a word line designated by an external address signal is set to a potential higher than the supply potential Vcc. This is because a potential lower than the supply potential Vcc by the threshold voltage Vth is transmitted to a source electrode connected to a memory cell capacitor, if the potentials of a drain electrode connected to a bit line and of a gate electrode connected to the word line of an n channel MOS transistor included in the memory cell are both at the supply potential Vcc. When the supply potential Vcc at the drain electrode is to be transmitted to the source electrode, the potential at the gate electrode must be boosted at least to Vcc+Vth. Recently, a method has been employed in which a boosted potential Vpp higher than the supply potential Vcc is generated by a charge pump or the like based on the supply potential Vcc, the generated boosted voltage is stored in a capacitor and the capacitor is used as a power supply for such a circuit for boosting the word line, as a word line drive signal generating circuit providing a word line drive signal.
FIG. 33 is a block diagram showing a conventional DRAM (Dynamic Random Access Memory). Referring to FIG. 33, row selecting circuitry of the DRAM includes an RAS buffer 1, a row address buffer 2, and a predecoder 3 receiving an output from the row address buffer 2. RAS buffer 1 receives an external row address strobe signal ext/RAS and provides a row address strobe signal /RAS having the same logic as the external row address strobe signal ext/RAS. Row address buffer 2 receives the row address strobe signal /RAS from RAS buffer 1 and external address signals A.sub.0 to A.sub.5, latches the address signals A.sub.0 to A.sub.5 as a row address when the row address strobe signal /RAS is activated (when it attains to L level), and provides row address signals RA.sub.0, /RA.sub.0 to RA.sub.5, /RA.sub.5 having the same and complementary logics as to the address signals A.sub.0 to A.sub.5.
Predecoder 3 includes partial decoders 4, 5 and 6 each receiving 2 bits (complementarily 4 bits) of address signals from row address buffer 2. Partial decoder 4 receives row address signals RA.sub.0, /RA.sub.0, RA.sub.1, /RA.sub.1 from row address buffer 2 and the row address strobe signal /RAS from RAS buffer 1, and provides row predecode signals X.sub.0, X.sub.1, X.sub.2 and X.sub.3 one of which attains to H level at the supply potential Vcc while the remaining three attain to the L level based on the logics of the row address signals RA.sub.0, /RA.sub.0 and RA.sub.1, /RA.sub.1 when the row address strobe signal /RAS is at the L level, and all of which attain to the L level when the row address strobe signal /RAS is at the H level. Partial decoder 5 receives row address signals RA.sub.2, /RA.sub.2 and RA.sub.3, /RA.sub.3 from row address buffer 2 and provides row predecode signals X.sub.4, X.sub.5, X.sub.6 and X.sub.7, one of which attains to the H level at the supply potential Vcc while the remaining three attain to L level, based on the logics of row address signals RA.sub.2, /RA.sub.2 and RA.sub.3, /RA.sub.3. Partial decoder 6 receives row address signals RA.sub.4, /RA.sub.4 and RA.sub.5, /RA.sub.5 from the row address buffer 2 and provides row predecode signals X.sub.8, X.sub.9, X.sub.10 and X.sub.11, one of which attains to the H level at the supply potential Vcc while the remaining three attain to the L level based on the logics of the row address signals RA.sub.4, /RA.sub.4 and RA.sub.5, /RA.sub.5.
The row selecting circuitry further includes a boosted potential generating circuit 7 generating a prescribed high potential, and a row decoder group 9 receiving the boosted potential from the boosted potential generating circuit 7 and an output from predecoder 3.
Boosted potential generating circuit 7 operates, receiving the supply potential Vcc of, for example, 3 V, and provides a boosted potential Vpp of, for example, 5 V, which is higher than the supply potential Vcc by about twice the threshold voltage Vth of the n channel MOS transistor used in the memory cell, to a boosted potential node 8. Row decoder group 9 includes 64 row decoders 10. Each row decoder 10 operates receiving the boosted potential Vpp from boosted potential generating circuit 7, receives one of the predecode signals X.sub.0, X.sub.1, X.sub.2 and X.sub.3 from partial decoder 4, one of X.sub.4, X.sub.5, X.sub.6 and X.sub.7, and one of X.sub.8, X.sub.9, X.sub.10 and X.sub.11, that is, a total of three row predecode signals and provides a row decode signal RD and a row decode signal /RD which attain to the boosted potential Vpp and the ground potential, respectively, when all these three signals attain to the H level at the supply potential Vcc.
Word line drive signal generating circuit 11 operates receiving the boosted potential Vpp from boosted potential generating circuit 7, receives the row address strobe signal /RAS having the swing of the supply potential Vcc from RAS buffer 1, and provides a word line drive signal RX which attains from the ground potential to the boosted potential Vpp after a prescribed time from the change of the row address strobe signal /RAS from the H level to the L level.
Word driver group 12 includes 64 word drivers 13 provided corresponding to respective word lines in memory cell array 32. Word driver 13 receives row decode signals RD and /RD from row decoder 10 and word line drive signal RX from word line drive signal generating circuit 11. When row decode signal RD attains to the H level at the boosted potential Vpp, /RD attains to the L level and word line drive signal RX attains to the boosted potential Vpp, it raises the potential WL of the corresponding word line 14 to the boosted potential Vpp.
The column selecting circuitry of the DRAM includes a CAS buffer 15, a column address buffer 16 and a column predecoder 17 receiving an output from column address buffer 16. CAS buffer 15 receives an external column address strobe signal ext/CAS and provides a column address strobe signal /CAS having the same logic as the column address strobe signal ext /CAS. Column address buffer 16 receives column address strobe signal /CAS from CAS buffer 15 and external address signals A.sub.0 to A.sub.5, latches the address signals A.sub.0 to A.sub.5 as a column address when the column address strobe signal /CAS is activated (when it attains to the L level), and provides column address signals CA.sub.0, /CA.sub.0 to CA.sub.5, /CA.sub.5 having the same and complementary logics as to the address signals A.sub.0 to A.sub.5.
Column predecoder 17 includes three partial decoders 18, 19 and 20.
Partial decoder 18 receives column address signals CA.sub.0, /CA.sub.0 and CA.sub.1, /CA.sub.1 from column address buffer 16 and provides column predecode signals Y.sub.0, Y.sub.1, Y.sub.2 and Y.sub.3, one of which attains to the H level at the supply potential Vcc and remaining three of which attain to the L level based on the logics of the column address signals CA.sub.0, /CA.sub.0 and CA.sub.1, /CA.sub.1. Partial decoder 19 receives column address signals CA.sub.2, /CA.sub.2, and CA.sub.3, /CA.sub.3 from column address buffer 16 and provides column predecode signals Y.sub.4, Y.sub.5, Y.sub.6 and Y.sub.7, one of which attains to the H level of the supply potential Vcc and remaining three of which attain to the L level based on the logics of the column address signals CA.sub.2, /CA.sub.2 and CA.sub.3, /CA.sub.3.
Partial decoder 20 receives column address signals CA.sub.4, /CA.sub.4 and CA.sub.5, /CA.sub.5 from column address buffer 16 and provides column predecode signals Y.sub.8, Y.sub.9, Y.sub.10 and Y.sub.11, one of which attains to the H level at the supply potential Vcc and remaining three of which attain to the L level based on the logics of the column address signals CA.sub.4, /CA.sub.4 and CA.sub.5, /CA.sub.5.
Column selecting circuitry further includes a column decoder group 21 receiving an output from column predecoder 17 and 64 I/O gate circuits 30 receiving an output from column decoder group 21. Column decoder group 21 includes 64 column decoders 22 each receiving one of the column predecode signals Y.sub.0, Y.sub.1, Y.sub.2 and Y.sub.3 from column predecoder 17, one of Y.sub.4, Y.sub.5, Y.sub.6 and Y.sub.7, and one of Y.sub.8, Y.sub.9, Y.sub.10 and Y.sub.11, that is, a total of three column predecode signals, and provides a column selecting signal CSL which attains to the supply potential Vcc when all received three predecode signals attain to the H level at the supply potential Vcc.
I/O gate circuit 30 includes n channel MOS transistors 24 and 25, receives a column selecting signal CSL from column decoder group 21. When the column selecting signal CSL is at H level, it connects bit line 26 to I/O line 27 and bit line 28 to I/O line 29. I/O gate circuit 30 is included in an I/O control circuit 23, which I/O control circuit 23 includes a sense amplifier 31 connected between bit lines 26 and 28 in memory cell array 32 for detecting and amplifying the potential difference between the potential BL of bit line 26 and potential /BL of bit line 28. In memory cell array 32, memory cells 33 provided at crossings between word line 14 and bit lines 26 and 28 are arranged in a matrix.
FIG. 34 is a specific circuit diagram of row decoder 10 and word driver 13 of FIG. 33. Row decoder 10 includes a p channel MOS transistor 10a connected between a supply potential node 34 to which supply potential Vcc is applied and a first node 10b, and receiving one row predecode signal X.sub.A of row predecode signals X.sub.0, X.sub.1, X.sub.2 and X.sub.3 from partial decoder 4 at its gate electrode; an n channel MOS transistor 10c having its drain electrode connected to the first node 10b and receiving at its gate electrode the row predecode signal X.sub.A ; an n channel MOS transistor 10d having its drain electrode connected to the source electrode of n channel MOS transistor 10c and receiving at its gate electrode one row predecode signal X.sub.B out of row predecode signals X.sub.4, X.sub.5, X.sub.6 and X.sub.7 from partial decoder 5; and an n channel MOS transistor 10e connected between the source electrode of n channel MOS transistor 10d and a ground potential node 35 to which the ground potential is applied, and receiving at its gate electrode one row predecode signal X.sub.C of row predecode signals X.sub.8, X.sub.9, X.sub.10 and X.sub.11 from partial decoder 6. Combinations of row predecode signals X.sub.A, X.sub.B and X.sub.C differ from row decoder to row decoder, and there are 64 different combinations of predecode signals.
Row decoder 10 further includes a p channel MOS transistor 10f connected between supply potential node 34 and first node 10b, and an inverter 10g receiving a signal from the first node 10b and provides an inverted signal thereof. Inverter 10g includes a p channel MOS transistor 10ga having its source electrode connected to supply potential node 34 and its gate electrode connected to the first node 10b, and an n channel MOS transistor 10gb connected between the drain electrode of p channel MOS transistor 10ga and ground potential node 35 and having its gate electrode connected to the first node 10b.
Row decoder 10 further includes a level converting circuit 10h for converting the signal level of H level. The level converting circuit 10h operates receiving the boosted potential Vpp from boosted potential node 8, receives a signal having the amplitude of supply potential Vcc from the first node 10b and from inverter 10g, and provides a row decode signal RD of the amplitude of the boosted potential Vpp. Level converting circuit 10h includes a p channel MOS transistor 10hc connected between boosted potential node 8 and output node 10ha and having its gate electrode connected to a complementary output node 10hb; a p channel MOS transistor 10hd connected between boosted potential node 8 and complementary output node 10hb and its gate electrode connected to output node 10ha; an n channel MOS transistor 10he connected between output node 10ha and ground potential node 35 and having its gate electrode connected to the first node 10b; and an n channel MOS transistor 10hf connected between complementary output node 10hb and ground potential node 35 and receiving at its gate electrode a signal from inverter 10g.
Word driver 13 includes an n channel MOS transistor 13a connected between word line drive signal generating circuit 11 (signal RX) and word line 14; an n channel MOS transistor 13bconnected between word line 14 and ground potential node 35 and having its gate electrode connected to the first node 10b of row decoder 10; and an n channel MOS transistor 13c connected between output node 10ha of row decoder 10 and the gate electrode of n channel MOS transistor 13a and having its gate electrode connected to boosted potential node 8.
The operation for selecting a memory cell of the DRAM having the above structure will be described with reference to the timing chart of FIG. 35. First, as shown in FIG. 35 (c), address signals A.sub.0 to A.sub.5 are externally applied, and when external row address strobe signal ext/RAS falls from the supply potential Vcc to the ground potential at time t.sub.0 as shown in FIG. 35(a), RAS buffer 1 receives external row address strobe signal ext/RAS and provides a row address strobe signal /RAS which falls from the supply potential Vcc to the ground potential in synchronization with the row address strobe signal ext/RAS. Row address buffer 2 receiving the row address strobe signal /RAS latches the address signals A.sub.0 to A.sub.5 as a row address and provides row address signals RA.sub.0 to RA.sub.5 and row address signals /RA.sub.0 to /RA.sub.5 having the same and complementary logics as to address signals A.sub.0 to A.sub.5 and having the amplitude of supply potential Vcc.
Partial decoder 4 in row predecoder 3 receives row address signals RA.sub.0, /RA.sub.0, RA.sub.1, and /RA.sub.1 from row address buffer 2 and provides row predecode signals X.sub.0, X.sub.1, X.sub.2 and X.sub.3 of the amplitude of the supply potential Vcc. Based on the logics of row address signals RA.sub.0, /RA.sub.0, RA.sub.1 and /RA.sub.1, one of the four row predecode signals X.sub.0, X.sub.1, X.sub.2 and X.sub.3 is set to the H level and the remaining three are set to the L level. Partial decoders 5 and 6 receive row address signals RA.sub.2, /RA.sub.2, RA.sub.3, /RA.sub.3 and RA.sub.4, /RA.sub.4, RA.sub.5, /RA.sub.5 from row address buffer 2 in the similar manner, and provide row predecode signals X.sub.4, X.sub.5, X.sub.6, X.sub.7 and X.sub.8, X.sub.9, X.sub.10 based on the logics of these signals, respectively.
64 row decoders 10 in row decoder group 9 each receives one signal X.sub.A of row predecode signals X.sub.0, X.sub.1, X.sub.2 and X.sub.3 from partial decoder 4, one signal X.sub.B of row predecode signals X.sub.4, X.sub.5, X.sub.6 and X.sub.7 from partial decoder 5 and one signal X.sub.C of row predecode signals X.sub.8, X.sub.9, X.sub.10 and X.sub.11 from partial decoder 6. Only one of 64 row decoders 10 receives row predecode signals X.sub.A, X.sub.B and X.sub.C which are all at the H level, and remaining 63 row decoders 10 receive row predecode signals X.sub.A, X.sub.B and X.sub.C, at least one of which is at the L level.
In row decoder 10 receiving row predecode signals X.sub.A, X.sub.B and X.sub.C all at the H level, p channel MOS transistor 10a receiving at its gate electrode the row predecode signal X.sub.A is rendered non-conductive, and n channel MOS transistor 10c is rendered conductive. Similarly, n channel MOS transistor 10d receiving at its gate electrode the row predecode signal X.sub.B is rendered conductive, and n channel MOS transistor 10e receiving at its gate electrode the row predecode signal X.sub.C is rendered conductive. Accordingly, the first node 10b is coupled to ground potential node 35, and the potential /RD of the first node 10b attains to the ground potential. As a result, n channel MOS transistor 10hein signal level converting circuit 10h receiving the potential /RD at the gate electrode and n channel MOS transistor 13b in word driver 13 are rendered non-conductive.
Inverter 10g receives the potential /RD of the first node 10b which is at the ground potential, and provides a signal at the supply potential Vcc. In signal level converting circuit 10h, n channel MOS transistor 10hf receiving at its gate electrode the output of inverter 10g is rendered conductive, complementary output node 10hb and ground potential node 35 are coupled, and the potential of complementary output node 10hb attains to the ground potential. The p channel MOS transistor 10hc receiving at its gate electrode the potential of complementary output node 10hb is rendered conductive, and thus boosted potential node 8 is coupled to output node 10ha. The potential RD of output node 10ha attains to the boosted potential Vpp at time t.sub.1 as shown in FIG. 35(b), and p channel MOS transistor 10hd receiving at its gate the potential RD is rendered non-conductive.
The potential at the gate electrode of n channel MOS transistor 13a in word driver 13 rises as it receives the row decode signal RD at the boosted potential Vpp from output node 10ha, and when the potential at the gate electrode attains to a potential lower than the boosted potential Vpp by the threshold potential Vth of n channel MOS transistor 13c, the n channel MOS transistor 13c is rendered non-conductive, since the voltage between the gate and the source becomes lower than the threshold voltage Vth. Word line drive signal generating circuit 11 receives the row address strobe signal /RAS which has been fallen to the L level at time t.sub.0 from RAS buffer 1 and provides a word line drive signal RX which rises from the ground potential to the boosted potential Vpp at time t.sub.2 after a prescribed time period. In word driver 13, n channel MOS transistor 13a receives the word line drive signal RX. By capacitive coupling of the gate capacitance, the potential at the gate electrode of n channel MOS transistor 13a rises and boosted higher than the boosted potential Vpp by at least the threshold voltage Vth of n channel MOS transistor 13a. The word line drive signal RX is transmitted to word line 14, and the potential WL of word line 14 attains to the boosted potential Vpp at time t.sub.3 as shown in FIG. 35(f).
In row decoder 10 in which at least one of the row predecode signals X.sub.A, X.sub.B and X.sub.C is at the L level, before time t.sub.0 at which row address strobe signal /RAS falls to the L level, row predecode signal X.sub.A is at the L level, p channel MOS transistor 10a is conductive and n channel MOS transistor 10c is non-conductive. Therefore, the potential /RD of the first node 10b is at the supply potential Vcc level. After that time, since at least one of row predecode signals X.sub.A, X.sub.B and X.sub.C is at the L level, one of the n channel MOS transistors 10c, 10d and 10e is at the non-conductive state, and the potential /RD of the first node 10b is kept at the supply potential Vcc. The n channel MOS transistor 10he receiving at its gate the potential /RD and the n channel MOS transistor 13b are rendered conductive, output node 10ha is coupled to the ground potential node 35, word line 14 is coupled to the ground potential node 35, and the potential RD of output node 10ha and the potential WL of the word line attain to the ground potential.
Inverter 10g receives the potential of the first node 10b and provides a signal at the ground potential. The n channel MOS transistor 10hf receiving at its gate the output signal of inverter 10g is rendered non-conductive, while the p channel MOS transistor 10hb receiving at its gate the potential RD of the output node 10ha at the ground potential is rendered conductive. Boosted potential node 8 is coupled to the complementary output node 10hb, the potential of the complementary output node 10hb attains to the boosted potential Vpp, and p channel MOS transistor 10hc receiving this potential at its gate electrode is rendered non-conductive. In word driver 13, n channel MOS transistor 13a receives at its gate electrode the row decode signal RD at the ground potential from output node 10ha, and is rendered non-conductive. As a result, even when a word line drive signal RX which rises from the ground potential to the boosted potential Vpp at time t.sub.2 is input from word line drive signal generating circuit 11, the potential WL at word line 14 is kept at the ground potential.
The data which has been stored is output from memory cell 33 connected to word line 14 which has a potential risen to the boosted potential Vpp to bit line 26 or 28. The potentials BL and /BL of bit lines 26 an 28 are set to the intermediate potential (1/2) Vcc between the supply potential Vcc and the ground potential in advance at the standby state. Assume that the data which has been stored in memory cell 33 is provided to bit line 26. If the data is at the H level, charges flow from memory cell 33 to bit line 26, and the potential BL of bit line 26 slightly rises from the intermediate potential (1/2) Vcc. If the data is at the L level, charges flow in from bit line 26 to memory cell 33, and the potential BL of bit line 26 slightly lowers from the intermediate potential (1/2) Vcc.
Sense amplifier 31 (see FIG. 33) connected between bit lines 26 and 28 amplifies the potential difference between the potential BL of the bit line 26 which has changed slightly from the intermediate potential (1/2) Vcc and the potential /BL of the bit line 28 which is kept at the intermediate potential (1/2) Vcc. If the potential difference is negative, the potential BL of the bit line 26 is lowered to the ground potential and the potential /BL of the bit line is raised to the supply potential Vcc. If the potential difference is positive, the potential BL of the bit line 26 is raised to the supply potential Vcc and the potential /BL of bit line 28 is lowered to the ground potential.
When address signals A.sub.0 to A.sub.5 are externally applied and the external column address strobe signal ext/CAS falls from the H level at the supply potential Vcc to the L level as shown in FIG. 35(b) at time t.sub.4, CAS buffer 15 receives the external column address strobe signal ext/CAS and provides a column address strobe signal /CAS which falls from the H level at the supply potential Vcc to the L level, in synchronization therewith. In accordance with the column address strobe signal /CAS, column address buffer 16 latches address signals A.sub.0 to A.sub.5 as a column address, and provides column address signals CA.sub.0 to CA.sub.5 of the amplitude of the supply potential Vcc (H level or L level) of the same logic as the address signals A.sub.0 to A.sub.5 and column address signals /CA.sub.0 to /CA.sub.5 of the complementary logics (L level or H level).
Partial decoder 18 in column predecoder 17 receives column address signals CA.sub.0, /CA.sub.0, CA.sub.1, /CA.sub.1 from column address buffer 16 and provides column predecode signals Y.sub.0, Y.sub.1, Y.sub.2 and Y.sub.3 of the amplitude of the supply potential Vcc. Based on the logics of column address signals CA.sub.0, /CA.sub.0, CA.sub.1, /CA.sub.1, only one of the four column predecode signals Y.sub.0, Y.sub.1, Y.sub.2 and Y.sub.3 is set to the H level and the remaining three are set to the L level. Partial decoders 19 and 20 similarly receive column address signals CA.sub.2, /CA.sub.2, CA.sub.3, /CA.sub.3 and CA.sub.4, /CA.sub.4, CA.sub.5, /CA.sub.5 from column address buffer 16, respectively, and provide column predecode signals Y.sub.4, Y.sub.5, Y.sub.6 and Y.sub.7 and Y.sub.8, Y.sub.9, Y.sub.10 and Y.sub.11 based on the logics of these signals, respectively.
Each of 64 column decoders 22 in column decoder group 21 receives one signal Y.sub.A out of column predecode signals Y.sub.0, Y.sub.1, Y.sub.2 and Y.sub.3 from partial decoder 18, one signal Y.sub.B out of column predecode signals Y.sub.4, Y.sub.5, Y.sub.6 and Y.sub.7 from partial decoder 19 and one signal Y.sub.C out of column predecode signals Y.sub.8, Y.sub.9, Y.sub.10 and Y.sub.11 from partial decoder 20. Only one decoder 22 of 64 column decoders 22 receives three column predecode signals Y.sub.A, Y.sub.B and Y.sub.C which are all at the H level. At least one of the column predecode signals Y.sub.A, Y.sub.B and Y.sub.C received by the remaining 63 column decoder 22 is at the L level. The column decoder 22 in which three column predecode signals Y.sub.A, Y.sub.B and Y.sub.C are all at the H level provides a column selection signal CSL which attains to the H level at the supply potential Vcc at time t.sub.5 as shown in FIG. 35(g), and remaining 63 column decoders 22 provide column selecting signal CSL at the L level.
The n channel MOS transistors 24 and 25 in I/O gate circuit 30 receiving the column selecting signal CSL at the H level from the column decoder 22 are rendered conductive, while n channel MOS transistors 24 and 25 in I/O gate circuit 30 receiving the column selecting signal CSL of the L level from column decoder 22 are kept non-conductive. Bit lines 26 and 28 connected to the n channel MOS transistors 24 and 25 which are rendered conductive are coupled to I/O lines 27 and 29, and hence data of memory cell 33 is provided to the I/O line.
In the conventional DRAM described above, the potential WL of word line 14 is raised to a boosted potential Vpp (.apprxeq.Vcc+2Vth) which is higher than the supply potential Vcc by about twice the threshold voltage Vth of the n channel MOS transistor constituting memory cell 33. Word line drive signal RX from word line drive signal generating circuit 11 is boosted from the ground potential to the boosted potential Vpp, and by utilizing the fact that the potential of the gate electrode of n channel MOS transistor 13a in word driver 13 becomes higher than the boosted potential Vpp by the threshold voltage Vth of n channel MOS transistor 13a due to capacitive coupling, the boosted potential Vpp is transmitted to word line 14 (self boosting operation). In order to quickly boost the potential at the gate electrode of n channel MOS transistor 13a to be higher than Vpp+Vth so as to quickly raise the potential WL of word line 14 to the boosted potential Vpp, the row decode signal RD at the boosted potential Vpp is input to word driver 13 and the potential at the gate electrode of n channel MOS transistor 13a is set not at the supply potential Vcc but a potential Vpp-Vth (.apprxeq.Vcc+Vth) which is higher than the supply potential Vcc and lower than the boosted potential Vpp by the threshold voltage Vth of n channel MOS transistor 13c.
In order to provide a row decode signal RD having the amplitude of the boosted potential Vpp, a signal level converting circuit 10h is necessary for row decoder 10 to convert a signal having the amplitude of supply potential Vcc to a signal having the amplitude of the boosted potential Vpp. However, in the conventional DRAM described above, signal level converting circuit 10h is provided for each row decoder 10, which results in large layout area of the row decoder group 9.
FIG. 36 shows a schematic layout of row decoder 10 and word driver 13 of the conventional of the DRAM. The reference numeral 40 denotes an area in which memory cell array 32 is formed, 41 denotes an area in which word drivers 13 are formed, and 42 and 43 denote areas in which row decoders 10 are formed. More specifically, 42 denotes an area in which a level converting circuit 10h which operates with the boosted potential Vpp is formed, and 43 denotes an area in which other circuits 10a to 10g are formed. As shown in FIG. 36, the area 42 in which level converting circuit 10h is to be formed occupies about one third of the whole area in which circuits (row decoder 10 and word driver 13) for selecting the word line are to be formed. As a result, though the word line can be quickly raised to the boosted potential Vpp, the existence of level converting circuit 10h increased the chip area.